1.
Fast
enhancement of validation test sets for improving the stuck-at fault coverage
of RTL circuits(MAY2009)
2.
Bit-Swapping
LFSR and scan-chain ordering :A novel technique for peak-and average-power
reduction in scan-based BIST(MAY2009)
3.
A
low power low area multiplier based on shift and add architecture (FEB2009)
4.
Deviation
based LFSR reseeding for test data compression(FEB2009)
5.
Combining
data reuse with data level parallelization
for FPGA targeted hardware compilation :A geometric programming frame work(SEP2008)
6.
Fault
secure encoder and decoder for nano memory applications(SEP2007)
7.
A
TREE based novel representation for 3D block packing(MAY2007)
8.
Low
power scan design using first level supply gating(FEB2007)
9.
Improving
linear test data compression(NOV2006)
10.
New
for untestable fault identification in
sequential circuits(JAN2006)
11.
New
and improved BIST diagnosis method from combinatorial group testing theory(MAR2006)
12.
A
high efficiency digital synchronous buck converter power delivery system based
on finite state machine(MAR2006)
13.
Design
specific path delay testing in look up table based FPGA(MAY2006)
14.
A
combined gate replacement and input vector control approach for leakage current
reduction(FEB2006)
15.
X
masking during logic bist and its impact on defect coverage(FEB2006)
16.
Energy
management for battery powered
reconfigurable computing platforms(FEB2006)
17.
Auto
scan :A scan design without external scan inputs or outputs (SEP2005)
18.
Accumulator
based test generation for robust sequential fault(SEP2005)
19.
Optimization
techniques for FPGA based wave pipelined DSP blocks(JUL2005)
20.
Leakage
current reduction in CMOS circuit using I/P vector control(FEB2004)
21.
Weighted
PSEUDO-RANDOM hybrid bist(DEC2004)
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